The present invention relates generally to A/D conversion, and in particular to a method and arrangement for A/D conversion offset error correction and to an A/D conversion offset error compensated decoding method and arrangement.
An A/D converter typically has a resolution of 10-14 bits. However, not all of these bits are valid, since there normally is a zero offset error in the range of 4-6 times the least significant bit. This offset error typically varies rather slowly over time and may, in a first approximation, be considered as a constant that characterizes the A/D converter and differs from one converter to another. A problem caused by this offset error is that it may lead to incorrect decoding of bits or symbols in decoders if the noise level is sufficiently high.
An object of the present invention is to provide an A/D conversion offset error correction method and arrangement that estimate the offset error and subtract it from the A/D converted signal before this signal is decoded.
Another object of the present invention is to provide an A/D conversion offset error compensated decoding method and arrangement.
These object is solved in accordance with the attached patent claims.
Briefly, the present invention is based on the observation that the decoding process itself may be used to determine the offset error. By subtracting a digital signal that is equivalent to the decoded signal from the A/D converted signal, the remaining digital signal will only contain the offset error and noise. If this signal over is averaged time, the noise will average to zero, and only an estimate of the offset will remain. By subtracting this offset estimate from future A/D converted signals, decoding of this offset corrected signal will be more robust. Alternatively one may say that the SNR (signal to noise ratio) of the decoding process has been increased.